This circuit generates a pulse on the rising edge.

这个电路在上升沿时会产生一个脉冲。

We need to detect the signal change on the rising edge.

我们需要在上升沿检测信号的变化。

The counter increments on each rising edge of the clock cycle.

计数器在每个时钟周期的上升沿递增。

In digital circuits, the rising edge of a signal is very important.

在数字电路中，信号的上升沿非常重要。

This flip-flop is triggered on the rising edge of the clock signal.

这个触发器在时钟信号的上升沿时被激活。

It is used to initialize the interrupt trigger as rising edge.

它用来将中断初始化为上升沿触发。

The analog input signal is latched on the rising edge of CLK.

模拟输入信号在CLK的上升沿被锁存.

The analog input signal is latched on the rising edge of CLK .

模拟输入信号在CLK的上升沿被锁存。

If a mark is to be transmitted, the output goes high after the rising edge of the clock.

如果一个标志是要传输时，输出变为高电平后，在时钟的上升沿。

Data is read serially by the Driver IC on the input CLK rising edge once the STB input line goes low.

数据读取连续的驱动IC的输入时钟的上升沿一旦机顶盒输入线变低。