The analog input signal is latched on the rising edge of CLK.

模拟输入信号在CLK的上升沿被锁存.

The analog input signal is latched on the rising edge of CLK .

模拟输入信号在CLK的上升沿被锁存。

The output of the CLK pin will be set to the crystal frequency.

该CLK 引脚输出将被设置为晶振频率。

Proteins known as CLK, or clock, accumulate in the SCN throughout the day.

被称为CLK的蛋白，也读作clock，在一天中都在SCN中积累。

Data is read serially by the Driver IC on the input CLK rising edge once the STB input line goes low.

数据读取连续的驱动IC的输入时钟的上升沿一旦机顶盒输入线变低。

When enough PER accumulates, it deactivates the gene that makes CLK, eventually making us fall asleep.

当PER积累到足够的量，它会给制造CLK蛋白的基因一个负反馈，最终使我们进入梦乡。

Then, clock falls low, so PER concentrations also drop again, allowing CLK to rise, starting the cycle over.

之后，clock的浓度降低，PER的浓度也随之降低，使得CLK的浓度回升，开始了新一个轮回。

In these two modes the DATA and CLK pins should not be clocked to reduce noise in the captured pressure or temperature data.

在这两个数据和时钟引脚不应时钟频率为减少捕获的压力和温度数据的噪音模式。